A. Field of the Invention
The present invention relates to the field of wireless digital communication and, more particularly, to a software defined radio system that uses a multi-layered architecture to implement multiple standards, services and applications.
B. Description of the Prior Art
In general, frequency bandwidth is an expensive resource and many countries view it as common property. Because the usages of released frequency bands for different services in different regions are different, it is difficult to reuse the same equipment to communicate with equipment in other regions. Typically, wireless digital communication standards are implemented on different hardware platforms. For example, except for a dual-mode Global System for Mobile Communications (GSM) handset, a 900 MHz GSM handset can not be used in the region of 1800 MHz GSM. It is inefficient for users to travel among different regions when they can not enjoy the different services provided by different vendors serving those regions. As a result, users may have to carry several different purpose handsets to enable communication as they travel from one region to another.
FIG. 1 illustrates a wireless digital communication system 100 that embodies a conventional approach to implement a single communication standard. Signals are received by an antenna 102 and initially processed by a radio frequency (RF) subsystem 104 and an intermediate frequency (IF) subsystem 106. RF subsystem 104 and IF subsystem 106 implement waveform processing of analog signals, including analog signal mixing, filtering, amplifying, and gain control. The analog signals processed by RF subsystem 104 and IF subsystem 106 are then fed into an analog-to-digital converter (A/D) subsystem 108 for conversion into an equivalent digital signal representation.
In general, the digital signals output by A/D subsystem 108 are processed by a dedicated logic device 110 for fixed standard-specific and channel-specific functions such as modem, digital filtering and other dedicated signal processing. The output from the dedicated logic device 110 is placed on a bus 112. Signals from bus 112 are routed to a programmable logic device 114, digital signal processor (DSP) 116, and a microprocessor 118. By controlling the download of functionality into programmable logic device 114 and managing the data flow input and output of programmable logic device 114 new specific functions can be performed.
For lower processing rate applications, DSP 116 can be used to implement the functions of digital signaling processing. For higher processing rate applications, the programmable logic device 114 can be used to provide a hardwired solution to implement high bandwidth functions of digital signaling processing. Microprocessor 118 is a general-purpose microprocessor and is used to implement control functions. A software part 120 of FIG. 1 shows a control architecture of a conventional single-standard communication device. An operating system (OS) 122 plays the role of process management, and in general runs on microprocessor 118. An application 124 which executes a set of hardware/software functions is run under OS 122. If application 124 needs computational resources, at least one of programmable logic device 114, DSP 116, and microprocessor 118 is used to perform signal processing and create a data flow and control flow. By combining these resources, the application can run on the hardware platform and achieve a required performance.
FIG. 2 illustrates a wireless digital communication system 200 that is implemented in accordance with a conventional approach for implementing multiple communication standards. System 200 is configured similarly to system 100 except that it includes a dedicated logic device bank 202 to support different standard-specific, channel-specific, modem-specific and other signal processing functions. Signals are received by antenna 102 and initially processed by RF subsystem 104, IF subsystem 106, and A/D subsystem 108 for conversion to an equivalent digital signal representation. Logic device bank 202 receives the digital signals output by A/D subsystem 108. The output from logic device bank 202 is placed on bus 112 and routed to programmable logic device 114, DSP 116, or microprocessor 118. Typically dedicated logic device bank 202 is optimized to suit different wireless digital communication standards. Therefore, the conventional approach depicted in FIG. 2 to accommodate multiple standards has essentially combined disparate hardware and software resources separately optimized for each standard of interest. This platform results in poor efficiency in terms of size, cost and power consumption.
FIG. 3 illustrates a control architecture 300 for a conventional multiple standard communication equipment. OS 122 plays the role of process management, and in general runs on microprocessor 118. Thus each application 124 which executes a set of hardware/software functions is running under OS 122. The resource requirements for different standards, applications, and services are different. Since each application needs computational resources, either programmable logic device 114, DSP 116, or microprocessor 118 is provided to take care of signal processing and to create a data flow and control flow. Different products and services decide the required resources and combine them. After suitable combination, each application can run on the hardware platform and achieve the required performance. This architecture results in poor efficiency in terms of size, cost and power consumption.
FIG. 4 illustrates a relationship between efficiency and flexibility for different hardware devices. From the viewpoint of efficiency, a fixed-hardware resource such as an application-specific integrated circuit (ASIC) is highly efficient due to its design for a dedicated function. In general, highly configurable and programmable logic devices such as a microprocessor or a digital signal processor are inefficient with respect to both power and size. By analyzing the energy efficiency via MOPS/mW (million operations per milliWatt) among several computational units, there is an efficiency gap between the ASIC and the DSP.
FIG. 5 illustrates a wireless digital communication device 500, which comprises a digital down-converter (DDC) 518, a digital up-converter (DUC) 519, a software-programmable digital signal processor 502, a software-programmable microprocessor 504, a heterogeneous re-configurable multiprocessing logic circuit 506, and a bus 508 connecting digital signal processor 502, microprocessor 504, and multiprocessing logic circuit 506. Logic circuit 506 comprises a set of heterogeneous signal processing kernels 510, 512, and 514, and a re-configurable data router (not shown) interconnecting the heterogeneous signal processing kernels. The signal processing kernels and data routers are controlled by microprocessor 504 via control busses (not shown).
The platform embodied in device 500 enables the same hardware resources to be re-configured to provide more flexible delivery of arithmetic and control operations by usage of multiprocessing logic circuit 506. This device is constructed in accordance with a set of software modules each combined with hardware. Software kernels 510 are executable on multiprocessing logic circuit 506, software kernels 512 are executable on software-programmable digital signal processors 502, and software kernels 514 are executable on microprocessor 504. Executive code 516 further facilitates the management of the data flow input and output of logic circuit 506 and controls the data flow and control flow of all computational resources.
Device 500 is configured to support an efficient fixed-hardware resource such as an ASIC and maintain flexibility so it can be re-configured into different hardware. Logic circuit 506 may improve a trade-off between efficiency and flexibility for the purpose of multiple standards, applications and services. However, in this architecture, the local characteristic of the data router and memory built on logic circuit 506 and the bus scheme constrains upgrade and extension.